At their annual symposium, Intel presented innovations spanning desktop, Xeon, AI, and GPU sectors.
Intel’s FPGA spectrum got a refresh, emphasizing affordability, with their FPGA development software now adopting an open-source format, alongside the introduction of a processor blueprint grounded in the RISC-V model.
Kicking things off is the Agilex 3 series – compact, power-efficient FPGAs. Echoing the branding style of the Core desktop sequence, Agilex’s product hierarchy begins with 3 at the entry-level, advancing through 5, 7, and 9, indicating increasing prowess.
Two sub-categories, B-Series and C-Series, are incorporated under the Agilex 3 umbrella. B-Series FPGAs stand out with a denser I/O in a miniaturized package and run on minimal power, outdoing Intel’s traditional FPGA benchmarks. These are perfect for board-level operations, especially focusing on server management endeavors. On the other hand, C-Series is engineered for intricate FPGA projects, serving a myriad of sectors.
Making its debut for select early adopters is the Agilex 5 E-Series, set for wider release in early 2024. These extensions to the Agilex 5 ensemble promise superior energy efficiency and performance, a result of enhanced manufacturing techniques.
Following their May reveal, Intel’s Agilex 7 FPGAs equipped with R-Tile are now available, boasting advanced features like heightened CXL 2.0 and PCIe 5.0 throughput. Their CXL bandwidth capabilities notably outpace competitors.
Pivoting to software, Intel has made its proprietary Open FPGA Stack (OFS) software universally accessible. Designed as a foundational tool for FPGA creation, OFS provides both standard code resources and Linux-compatible, open-source drivers. Both Agilex and the Stratix 10 suite are OFS-compatible.
Intel has also spotlighted its Nios V chip design, rooted in the universally recognized RISC-V framework. The compact Nios V/c microcontroller is aimed at enhancing FPGA designs and synchronizing with the Quartus Prime Pro software toolset.
To round off, Intel unveiled the F2000X Infrastructure Processing Unit (IPU), colloquially termed a SmartNIC. Napatech, a frontrunner in the SmartNIC and IPU domain, will roll out the first consumer-ready versions.