Micron Debuts CXL 2.0 Memory Modules with Enhanced Features

Micron’s latest memory modules are in line with the advanced Compute Express Link 2.0 standards, offering improved security and heightened adaptability compared to its predecessors. Micron recently rolled out memory modules compatible with the updated 2.0 version of Compute Express Link (CXL). These units boast a maximum of 256GB of DRAM over a PCIe x8 channel.

At its core, CXL is an open-interface blueprint, widely acknowledged in the industry, designed to facilitate memory content sharing across machines. It leverages the infrastructure of PCI Express, enabling cohesive memory interactions between a CPU and other devices, such as hardware accelerators or even another CPU.

Typically, PCIe focuses on direct communication lines, like those from SSD to memory. However, CXL aims to evolve to multi-point communication, even though its current capacity limits it to direct communication. The inception of CXL began in early 2019. Its market introduction was postponed due to the necessity of an accelerated PCIe bus and the integral backing from CPU giants, Intel and AMD. Only their latest CPU editions are CXL-compatible.

At present, the focus is primarily on coupling DRAM with a PCIe route, which Micron’s CZ120 memory expansion modules showcase. These units are available in sizable 128GB and 256GB versions, harnessing a unique dual-channel memory structure that can achieve a peak 36GB/s bandwidth.

According to Ryan Baxter, Micron’s senior director for data centers, security enhancements are the highlight of this iteration. “CXL 2.0 introduces a plethora of security enhancements, many of which were absent or unsupported in the 1.1 version,” Baxter mentioned.

Given the inter-server communication, security is paramount. The refined CXL 2.0 now incorporates universal communication encryption, thanks to in-built hardware acceleration in CXL controllers. Consequently, hardware manufacturers need not integrate encryption security independently. Baxter indicated that the compromised security in CXL 1.1 limited its deployment, with many opting for experimental or lower-capacity memory uses. A few might have employed CXL 1.1 for internal operations, but many deferred ambitious projects in anticipation of 2.0.

Moreover, CXL 2.0 will back persistent memory—rapid like DRAM but retaining data like NAND flash. This version facilitates unique PMEM support among a chain of combined assets.

Micron envisions two pivotal applications for CXL 2.0: supplying supplementary memory to CPUs under extensive operations and catering to bandwidth-heavy tasks, given that PCIe’s design surpasses memory slot speeds.

As for targeted workloads? “There’s noticeable traction for AI processes, including training and inference. Such tasks necessitate expansive memory around the CPU,” Baxter noted. He also referenced conventional applications, such as in-memory databases, which would gain from CXL 2.0’s memory expansion.

CXL’s trajectory is laden with intentional redundancy. Version 2.0 isn’t compatible with 1.1, and similarly, version 3.0, leveraging the subsequent PCIe generation, won’t align with 2.0. Baxter foresees widespread 2.0 adoption and availability to mature by 2025 at the earliest.